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| UT54ACS04/UT54ACTS04 Radiation-Hardened Hex Inverters FEATURES radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 14-pin DIP - 14-lead flatpack DESCRIPTION The UT54ACS04 and the UT54ACTS04 are hex inverters. The circuits perform the Boolean function Y = A. The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE INPUT A H L OUTPUT Y L H PINOUTS 14-Pin DIP Top View A1 Y1 A2 Y2 A3 Y3 VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD A6 Y6 A5 Y5 A4 Y4 14-Lead Flatpack Top View A1 Y1 A2 Y2 A3 Y3 VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD A6 Y6 A5 Y5 A4 Y4 LOGIC DIAGRAM LOGIC SYMBOL A1 A2 A3 A4 A5 A6 (1) (3) (5) (9) (11) (13) 1 (2) (4) (6) (8) (10) (12) Y1 Y2 Y3 Y4 Y5 Y6 A4 and A5 Y5 Y4 A3 Y3 A2 Y2 A1 Y1 Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 IEC Publication 617-12. A6 Y6 9 RadHard MSI Logic UT54ACS04/UT54ACTS04 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER Total Dose SEU Threshold2 SEL Threshold Neutron Fluence LIMIT 1.0E6 80 120 1.0E14 UNITS rads(Si) MeV-cm2/mg MeV-cm2/mg n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL VDD VI/O TSTG TJ TLS JC PARAMETER Supply voltage Voltage any pin Storage Temperature range Maximum junction temperature Lead temperature (soldering 5 seconds) Thermal resistance junction to case DC input current Maximum power dissipation LIMIT -0.3 to 7.0 -.3 to VDD +.3 -65 to +150 +175 +300 20 10 1 UNITS V V C C C C/W mA W II PD Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL VDD VIN TC PARAMETER Supply voltage Input voltage any pin Temperature range LIMIT 4.5 to 5.5 0 to VDD -55 to + 125 UNITS V V C RadHard MSI Logic 10 UT54ACS04/UT54ACTS04 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL PARAMETER Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS Input leakage current ACTS/ACS Low-level output voltage 3 ACTS ACS High-level output voltage 3 ACTS ACS Short-circuit output current 2 ,4 ACTS/ACS Output current10 (Sink) IOH Output current10 (Source) Ptotal IDDQ IDDQ Power dissipation 2, 8, 9 Quiescent Supply Current Quiescent Supply Current Delta ACTS VIN = VDD or VSS IOL = 8mA IOL = 100 A IOH = -8mA IOH = -100 A VO = VDD and VSS VIN = VDD or VSS VOL = 0.4V VIN = VDD or VSS VOH = VDD - 0.4V CL = 50pF VDD = 5.5V For input under test VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 Output capacitance 5 = 1MHz @ 0V = 1MHz @ 0V 15 15 pF pF 1.8 10 1.6 mW/ MHz A mA -8 mA .7VDD VDD - 0.25 -200 8 200 .5VDD .7VDD -1 1 0.40 0.25 CONDITION MIN MAX 0.8 .3VDD UNIT V VIH V IIN VOL A V VOH V IOS IOL mA mA 11 RadHard MSI Logic UT54ACS04/UT54ACTS04 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSSsat frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL tPHL tPLH Input to Yn Input to Yn PARAMETER MINIMUM 1 1 MAXIMUM 19 11 UNIT ns ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si) RadHard MSI Logic 12 |
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